1. Field
The following description relates to a stacked semiconductor package technique for stacking semiconductor chips on a chip basis.
2. Description of the Related Art
A new stacked semiconductor package technique that doubles memory capacity by, for example, stacking two identical memory semiconductor packages has been introduced. U.S. Pat. No. 6,242,285 discloses a method that has been implemented by an applicant of the present invention. The above prior art is advantageous in its implementation since pins on an upper chip are deformed and subsequently are directly bonded with pins on a lower chip.
However, some pins have been recently designed to have shorter lengths, so that ends of pins on an upper chip come to be relatively far apart from upper ends of pins on a lower chip. Consequently, after a soldering paste process, bonding is performed improperly, resulting in the occurrence of more defects.